Espressif Systems /ESP32-S3 /LCD_CAM /LCD_CLOCK

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Interpret as LCD_CLOCK

Description

LCD clock register

Fields

LCD_CLKCNT_N	f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
LCD_CLK_EQU_SYSCLK	1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
LCD_CK_IDLE_EDGE	1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.
LCD_CK_OUT_EDGE	1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.
LCD_CLKM_DIV_NUM	Integral LCD clock divider value
LCD_CLKM_DIV_B	Fractional clock divider numerator value
LCD_CLKM_DIV_A	Fractional clock divider denominator value
LCD_CLK_SEL	Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
CLK_EN	Set this bit to enable clk gate

Links

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